1m x 4 static ram cy7c1046b cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 may 24, 2001 1cy7c1046b features ? high speed ?t aa = 12 ns low active power ? 935 mw (max.) low cmos standby power (l version) ? 2.75 mw (max.) 2.0v data retention (400 w at 2.0v retention) automatic power-down when deselected ttl-compatible inputs and outputs easy memory expansion with ce and oe features functional description the cy7c1046b is a high-performance cmos static ram or- ganized as 1,048,576 words by 4 bits. easy memory expan- sion is provided by an active low chip enable (ce ), an active low output enable (oe ), and three-state drivers. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the four i/o pins (i/o 0 through i/o 3 ) is then written into the location specified on the address pins (a 0 through a 19 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the four input/output pins (i/o 0 through i/o 3 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1046b is available in a standard 400-mil-wide 32-pin soj package with center power and ground (revolution- ary) pinout. 14 15 l og i c bl oc k di agram pi n c on fi gurat i on a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 1m x 4 array i/o 3 i/o 2 a 0 a 11 a 13 a 12 a ce a a 16 a 17 1 2 3 4 5 6 7 8 9 10 12 21 22 25 24 23 28 27 26 top view soj 11 29 32 31 30 14 13 19 20 gnd a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 we v cc a 18 a 15 a 12 a 14 i/o 2 1046b?1 a 9 a 0 i/o 0 i/o 1 oe a 17 a 16 a 13 ce 1046b?2 a 9 a 18 16 15 17 18 gnd i/o 3 v cc a 10 a 11 a 19 nc a 10 a 19 selection guide 7c1046b-12 7c1046b-15 7c1046b-20 maximum access time (ns) 12 15 20 maximum operating current (ma) 170 150 130 maximum cmos standby current (ma) com?l 88 8 l version 0.5 0.5 0.5 shaded areas contain advance information.
cy7c1046b 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ?65 c to +150 c ambient temperature with power applied?55 c to +125 c supply voltage on v cc to relative gnd [1] ?0.5v to +7.0v dc voltage applied to outputs in high z state [1] ?0.5v to v cc + 0.5v dc input voltage [1] ?0.5v to v cc + 0.5v current into outputs (low)20 ma static discharge voltage>2001v (per mil-std-883, method 3015) latch-up current>200 ma operating range range ambient temperature [2] v cc commercial 0 c to +70 c 4.5v?5.5v electrical characteristics over the operating range parameter description test conditions 7c1046b-12 7c1046b-15 7c1046b-20 min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ?0.3 0.8?0.30.8?0.30.8 v i ix input load current gnd < v i < v cc ?1 +1 ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc 170 150 130 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 20 20 20 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 com?l 888ma l version 0.5 0.5 0.5 shaded areas contain advance information . capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 6pf c out i/o capacitance 6 pf note: 1. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 2. t a is the ?instant on? case temperature. 3. tested initially and after any design or process changes that may affect these parameters.
cy7c1046b 3 ac test loads and waveforms switching characteristics [4] over the operating range 7c1046b-12 7c1046b-15 7c1046b-20 parameter description min. max. min. max. min. max. unit read cycle t power v cc (typical) to the first access [5] 1 11 s t rc read cycle time 12 15 20 ns t aa address to data valid 12 15 20 ns t oha data hold from address change 3 33ns t ace ce low to data valid 12 15 20 ns t doe oe low to data valid 678ns t lzoe oe low to low z [7] 0 00ns t hzoe oe high to high z [6, 7] 678ns t lzce ce low to low z [7] 3 33ns t hzce ce high to high z [6, 7] 678ns t pu ce low to power-up 0 00ns t pd ce high to power-down 12 15 20 ns write cycle [8, 9] t wc write cycle time 12 15 20 ns t sce ce low to write end 8 10 15 ns t aw address set-up to write end 8 10 15 ns t ha address hold from write end 0 00ns t sa address set-up to write start 0 00ns t pwe we pulse width 8 10 12 ns t sd data set-up to write end 6 810ns t hd data hold from write end 0 00ns t lzwe we high to low z [7] 3 33ns t hzwe we low to high z [6, 7] 678ns notes: 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. this part has a voltage regulator which steps down the voltage from 5v to 3.3v internally. t power time has to be provided initially before a read/write operation is started. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the si gnal that terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 1046b?3 1046b?4 90%v cc 10%v cc vcc gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) output r1 481 ? r1 481 ? r2 255 ? r2 255 ? 167 ? equivalent to: venin equivalent 1.73v th rise time:1 v/ns fall time:1 v/ns
cy7c1046b 4 data retention characteristics over the operating range parameter description conditions [10] min. max unit v dr v cc for data retention 2.0 v i ccdr data retention current com?l v cc = v dr = 2.0v, ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v 200 a t cdr [3] chip deselect to data retention time 0 ns t r operation recovery time 200 s data retention waveform switching waveforms read cycle no. 1 [11, 12] read cycle no. 2 (oe controlled) [12, 13] notes: 10. no input may exceed v cc + 0.5v. 11. device is continuously selected. oe , ce = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. 1046b?5 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha 1046b?6 address data out 1046b?7 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current
cy7c1046b 5 write cycle no. 1 (ce controlled) [14, 15] write cycle no. 2 (we controlled, oe high during write) [14, 15] notes: 14. data i/o is high impedance if oe = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 16. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) 1046b?8 t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 16 1046b?9
cy7c1046b 6 document #: 38?00948?*a write cycle no. 3 (we controlled, oe low) [15] switching waveforms (continued) 1046b?10 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 16 ordering information speed (ns) ordering code package name package type operating range 12 CY7C1046B-12VC v33 32-lead (400-mil) molded soj commercial 15 cy7c1046b-15vc v33 32-lead (400-mil) molded soj 20 cy7c1046b-20vc v33 32-lead (400-mil) molded soj 12 cy7c1046bl-12vc v33 32-lead (400-mil) molded soj 15 cy7c1046bl-15vc v33 32-lead (400-mil) molded soj 20 cy7c1046bl-20vc v33 32-lead (400-mil) molded soj shaded areas contain advance information.
cy7c1046b ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram 32-lead (400-mil) molded soj v33 51-85033-a
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